1. Field of Invention
The present invention relates to the field of memories, and specifically to a voltage and timing calibration method used in a memory system.
2. Description of Related Arts
In an existing memory system, in order to reduce the loading of a memory controller and improve work timing, a memory buffer for buffering commands, addresses and data is generally set in a memory module. For example, in a memory system shown in FIG. 1, a fully buffer for buffering control signals and data signals in one is disposed, in which the fully buffer is connected in a communication manner to a memory controller and multiple memory chip units respectively. Still for example, in a memory system shown in FIG. 2, a control buffer for buffering control signals and data buffer for buffering data signals are disposed.
For a memory system disposed with any memory buffer, due to a low voltage (a supply voltage VDD≦1.5V) and a high speed (800-2133 Mbps) in operation, before a normal operation of the memory system, it is required to first calibrate timing and the voltage of the interfaces between the memory controller and the memory buffer, and between the memory buffer and each memory chip unit. In an existing process of calibrating the timing and the voltage, the memory buffer first sends control instructions, write timing and write data for the calibration, and adjusts timing and voltages at memory chips side of the memory buffer according to the data feedback from each memory chip, so as to implement calibration of the timing and the voltage between the memory chip side of the memory buffer and each memory chip. Afterwards, the memory controller sends the control instructions, the write timing and the write data for the calibration, and adjusts timing and voltages of the memory controller according to data feedback from the memory buffer, so as to implement calibration of the timing and the voltage between the memory controller and the memory controller side of the memory buffer. The calibration of the timing and the voltage between the memory buffer and each memory chip unit is first performed, so a signal generation unit for generating the control instructions, write timing and write data for calibration, and a timing and voltage calibration unit need to be disposed in the memory buffer. As shown in FIG. 1, likewise, a signal generation unit for generating the control instruction, write timing and write data for calibration, and a timing and voltage calibration unit also need to be disposed in the memory controller.
The signal generation unit for generating the control instructions, write timing and write data for calibration in the memory controller generally may be implemented by using a Basic Input/Output System (BIOS) (that is, a software manner), so that the design for the memory controller is simple and highly flexible. However, if the signal generation unit for generating the control instruction, write timing and write data for calibration in the memory buffer is also implemented in the software manner, a dedicated micro-processor needs to be disposed in the memory buffer. The dedicated micro-processor has simple functions but needs to output many control signals, resulting in complicated design, and further directly causing great increase in the cost. If pure hardware is used for the implementation, the circuit design for the memory buffer becomes complicated. Moreover, if problems are discovered after testing the manufactured memory buffer chip, the memory buffer chip needs to be re-designed and then manufactured, which prolongs the whole cycle of the memory buffer from design to pilot production, then to test, and finally to mass production.
Therefore, it is extremely necessary to improve the existing timing and voltage calibration method.